The present invention relates to a semiconductor inspection device used when a semiconductor device is inspected and in particular, to a semiconductor inspection device including a plurality of inspection circuits, which are different from each other and conducts a plurality of inspections, and an semiconductor inspection method therefor.
FIG. 9 is an external view showing a conventional semiconductor inspection device.
Referring to FIG. 9, a reference numeral 1 denotes a tester for testing a semiconductor device (hereinafter referred to simply as a tester); a reference numeral 2 a prober for inspecting a semiconductor device (hereinafter referred to simply as a prober); a reference numeral 3 a semiconductor inspection circuit (hereinafter referred to as a DUT board). The DUT board 3 builds therein peripheral circuits for outputting the electric characteristics of the semiconductor device 4 to be inspected (that is, a semiconductor device to be undergone inspection; hereinafter referred to as a DUT), and a conversion circuit for converting the electric characteristics into a measurable signal by a tester 1 for inspecting the semiconductor device and the like by a probe 5. The DUT 4 and the DUT board 3 are electrically connected to each other.
As shown in FIG. 10, the DUT board 3 is mounted with a semiconductor inspection circuit unit (hereinafter referred to as simply an inspection circuit unit) 3a, on which the probe (probe needle) 5 is provided. Then, when the DUT 4 is inspected the probe needle 5 is put into contact with (connected to) the DUT 4 to electrically connect the DUT 4 to the inspection circuit unit 3a. Here, the tester 1 for inspecting the semiconductor device is connected to the inspection circuit 3a via an interface cable 6a. 
Next, the operation of the conventional semiconductor inspection device shown in FIG. 9 will be described. When the DUT 4 is inspected, first, referring to FIG. 10 and FIG. 11, an inspection program and the semiconductor inspection circuit unit 3a are designed in accordance with what kind of inspection the DUT 4 conducts. Then, the DUT 4 (for example, wafer) is set on the DUT board 3 and a test (inspection) is started. After the inspection is started, a test start signal is sent to the prober 2 from the tester 1 (step ST1). When the prober 2 receives the test start signal, the prober 2 starts probing (step ST2). When the probing is started, first, the prober 2 controls the DUT board 3 and electrically connects the inspection circuit unit 3a to the DUT 4 by the probe 5. That is, the inspection circuit unit 3a is put into contact with the DUT 4 by the probe 5 (step ST3). When the inspection circuit unit 3a is contacted with the DUT 4, an inspection program (test program) is executed and the tester 1 sets inspection items (I) from 1 to J (J: an integer not smaller than 2) in accordance with the test program (step ST4). That is, the inspection is started after a plurality of inspection items are set (step ST5).
First, the tester 1 inspects the DUT 4 when the inspection item is I=1 and judges the inspection result (step ST6). If the inspection result is xe2x80x9cgoodxe2x80x9d, the process proceeds to the next inspection item (NEXT J: step ST7) and judges the inspection result in the same way. When the tester 1 ends inspecting the inspection items from 1 to J in this manner, that is, if the tester 1 judges that the DUT 4 is not bad in terms of all the inspection items from 1 to J, the tester 1 judges the DUT 4 to be a good product and sends a PASS signal to the prober 2 (step ST8). Then, the tester 1 ends the inspection and sends an END signal to the prober 2 (step ST9). When the prober 2 receives the END signal, the prober 2 controls the DUT board 3 and ends probing (step ST10).
Otherwise, if the DUT is judged to be xe2x80x9cbadxe2x80x9d, for example, it is judged that the DUT is bad in terms of the inspection item j (j: any one of integers from 1 to J), the tester 1 stops the test at a point of time of the inspection item j (when the DUT is judged to be bad) (step ST11). Then, the tester 1 sends a FAIL signal to the prober 2 (step ST12). This FAIL signal includes the inspection item j at which the DUT is judged to be bad. In response to the FAIL signal, the prober 2 marks the bad DUT 4 to designate a bad chip (step ST13), and further performs a map data processing for the bad DUT 4 on the basis of the FAIL signal (step ST14). After the tester 1 sends the FAIL signal, the tester 1 performs a bad category classification (binning) for the bad DUT 4 (step ST15) in accordance with how many inspection items j are and ends the inspection. As described above, the tester 1 sends the END signal to the prober 2 and the prober 2 ends probing.
The tests are repeatedly performed for the respective DUTs in the manner described above. In this manner, in the semiconductor inspection device shown in FIG. 9, the tester 1 and the prober 2 inspect and judge the DUTs in accordance with the inspection items, and the tester 1 stores the judgment results in the built-in storage circuit, and if the DUT is judged to be bad, the prober 2 marks the bad DUT to discriminate the bad chip.
Alternatively, as shown in FIG. 12, the DUT board 3 may be mounted with a plurality of inspection circuits. In FIG. 12, the first inspection circuit unit 3b and the second inspection circuit unit 3c are mounted on the DUT board 3. The first and the second inspection circuit units 3b and 3c are provided with the probes 5a and 5b, respectively, and the DUT 4a and the DUT 4b are mounted on the first and the second inspection circuit units 3b and 3c, respectively. The DUTs 4a and 4b are put into contact with the probes 5a and 5b, thereby electrically connecting them to the inspection circuit units 3a and 3b. The tester is connected to the first and the second inspection circuits 3b and 3c via interface cables 6b and 6c. The tester shown in FIG. 12 can test a plurality of DUTs at the same time and is referred to as a multiple tests related tester (indicated by a reference numeral 1a in FIG. 12). The first and the second inspection circuit units 3b and 3c, which have the same circuit configuration and are connected to pins of the tester 1a and are different from each other.
The tests (inspections) of the DUTs 4a and 4b when the above multiple tests related tester 1a will be described with reference to FIG. 13.
As described in FIG. 11, after the DUTs 4a and 4b are set on the DUT board 3 the test (inspection) is started. After the inspection is started, the tester 1a sends a test start signal to the prober 2 (step ST11). When the prober 2 receives the test start signal, the prober 2 starts probing (step ST12). When the prober 2 starts probing, first, the prober 2 controls the DUT board 3 to electrically connect the first and the second inspection circuit units 3b and 3c to the DUTs 4a and 4b by the probes 5a and 5, respectively. That is, the first and the second inspection circuit units 3b and 3c are put into electrical contact with the DUTs 4a and 4b by the probes 5a and 5, respectively (step ST13). When the first and second inspection circuit units 3b and 3c are electrically contacted with the DUTs 4a and 4b, an inspection program (test program) is executed and in accordance with the test program, the tester 1a sets the inspection items (I) from 1 to J, that is, sets a plurality of inspection items (step ST14) and starts the inspection (step ST15).
First, the tester 1a inspects the DUTs 4a and 4b in terms of the inspection item I=1 at the same time and judges the inspection results (steps ST16 and ST17). If the judgment reveals the DUT 4a to be xe2x80x9cgoodxe2x80x9d, the process proceeds to the next inspection item (step ST18) and the tester 1a judges the inspection result in the same way (step St18). Further, as to the DUT 4b, if the judgment reveals the DUT 4b to be xe2x80x9cgoodxe2x80x9d as well, the process proceeds to the next inspection item (step ST19) and the tester 1a judges the inspection result. When tester 1a ends the judgments in terms of the inspection items from 1 to J in this manner, that is, if the tester 1a judges that the DUTs 4a and 4b are not bad in terms of all the inspection items, the tester 1a judges the DUTs 4a and 4b to be good products and sends a PASS signal to the prober 2 (step ST20). Then, the tester 1a ends the inspection and sends an END signal to the prober 2 (step ST21). When the prober receives the END signal, the prober 2 controls the DUT board 2 and ends probing (step ST22).
Otherwise, if the tester 1a judges the DUT 4a to be xe2x80x9cbadxe2x80x9d, the tester 1a stops the test at a point of time where it judges that the DUT 4a is bad (at a point of time of the inspection item j) (step ST23), and performs a failure judgment processing (FAIL processing) (step ST24). Similarly, if the tester 1a judges the DUT 4b to be xe2x80x9cbadxe2x80x9d, the tester 1a stops the test at a point of time where it judges that the DUT 4b is bad (step ST25), and performs a FAIL processing. In the FAIL processing, if the DUT 4a is xe2x80x9cbadxe2x80x9d, the first FAIL signal indicating that the DUT 4a is bad is given to the prober 2 and the prober 2 marks the DUT 4a in accordance with the first FAIL signal to discriminate a bad chip (step ST26). Similarly, in the FAIL processing, if the DUT 4b is xe2x80x9cbadxe2x80x9d, the second FAIL signal indicating that the DUT 4b is bad is given to the prober 2 and the prober 2 marks the DUT 4a in accordance with the second FAIL signal to designate a bad chip (step ST27).
As described above, the tester 1a sends the FAIL signal and then performs a failure category classification (binning) for the bad DUT in accordance with how many inspection item j are (step ST28) and the tester 1a ends the inspection. Then, as described above, the tester 1a sends the END signal to the prober 2 and the prober 2 ends probing.
Since the tester 1a inspects the plurality of DUTs at the same time in a manner as described above, the matrix pins of the tester 1a increase in number in proportion to the number of DUTs as compared with the case where only one DUT is inspected, but an inspection processing capacity is improved.
The conventional semiconductor inspection device constructed as described above permits only the same inspection for one or a plurality of DUTs. Therefore, different inspections need different inspection devices, which requires the extremely long time for the inspections.
In other words, as the DUT increases its performance and operating speed in recent years, the semiconductor inspection device itself increases its performance and employs multiple pins, thereby making it possible to inspect the DUT in correspondence with its increased performance. However, such a semiconductor inspection device is very costly. For this reason, as the things stand, the DUT is inspected by the use of the inspection device in accordance with what kind of the inspection device inspection conducts.
However, as the DUT increases its performance and operating speed, the contents of inspection complicates and the inspection items becomes enormous. Accordingly, a plurality of inspection processes must go through to conduct the inspection of one DUT. In other words, it is extremely difficult to inspect all functions of the DUT by one inspection device and thus a plurality of inspection processes are required, which experiences not only a elongated inspection time of the DUT but also an increased cost.
The present invention has been made to solve the above-mentioned problems. An object of the present invention is to provide a semiconductor inspection device capable of performing a plurality of inspection processes at the same time and a semiconductor inspection method therefor.
Another object of the present invention is to provide a semiconductor inspection device capable of inspecting a semiconductor device in a short time at a low cost and a semiconductor inspection method therefor.
A semiconductor inspection device according to the present invention includes a semiconductor inspection circuit on which a semiconductor device is set in inspecting whether the semiconductor device is good or bad, and a tester for judging whether the semiconductor device is good or bad in accordance with the inspection output from the semiconductor inspection circuit, the semiconductor inspection circuit including semiconductor inspection circuit units from a first to an M-th (M: an integer not smaller than 2) which each inspect the semiconductor device in terms of the inspection items from a first to an M-th, which are different from each other, and wherein the tester judges the semiconductor device in terms of the inspection items from the first to the M-th in accordance with inspection outputs outputted from the semiconductor inspection circuit units from the first to the M-th to take them as judgment results from a first to an M-th.
As described above, according to the present invention, since the semiconductor inspection device includes the plurality of semiconductor inspection circuit units for each inspecting the inspection items in the semiconductor inspection circuit, which are different from each other and judges the semiconductor device in terms of the respective inspection items in accordance with the inspection outputs from the respective semiconductor inspection circuit units to produce a judgment result, it is possible to inspect the inspection items different from each other by one semiconductor inspection device. As a result, a plurality of inspection processes can substantially be assembled in to one inspection process. Further, since the plurality of inspection processes is substantially assembled into one inspection process, it is possible to inspect the semiconductor in a short time. Moreover, an increase in cost can be prevented because a specific semiconductor inspection device is unnecessary, that is, the inspection of the semiconductor device is performed at a low cost.
A semiconductor inspection device according to the present invention includes a semiconductor inspection circuit on which a semiconductor device is set in inspecting whether the semiconductor device is good or bad, and semiconductor inspection circuit units from the first to the M-th provided in the semiconductor inspection circuit and each inspect the semiconductor device in terms of inspection items from the first to the M-th (M: an integer not smaller than 2), which are different from each other, the method including the steps of: setting the semiconductor device on the m-th (m: an integer from 1 to M) semiconductor inspection circuit unit and judging whether the semiconductor device is good or bad in terms of the m-th inspection item to obtain the m-th judgment result; latching the m-th judgment result; and generating a good/bad result indicating whether the semiconductor device is good or bad on the basis of judgment results from the first to the M-th in accordance with a timing where the inspection in terms of the M-th inspection item is ended.